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PRL Project

A Methodology for Designing Asynchronous Circuits

by Rajit Manohar


    Professor Rajit Manohar, a new assistant professor in Electrical Engineering with a PhD from Caltech will speak on Monday. It is a way for him to get to know us and conversely. He does hardware synthesis and reasoning about hardware. A lot of what he does seems related to the Ensemble work.


    I will present the design methodology we use to design asynchronous circuits. We use a formal synthesis approach to transform a simple, sequential description into a highly complex concurrent system. I will talk about some of the new transformations we introduced in the design of a high-performance asynchronous MIPS processor.